1. Field of the Invention
The invention relates to differential amplifiers and, more particularly, to a differential amplifier having a characteristic of low distortion even during low voltage operation and applicable for mixer circuits and variable gain amplifier circuits.
2. Description of the Prior Art
It is a known fact that in recent years, portable electronic equipment including portable telephones has been widely used in society. Also, it is well known that in radio systems to which portable electronic equipment is applied, in order to ensure a long calling time during battery-driven operation of the equipment, there have been demands for a reduction of the driving voltage of the portable electronic equipment, which is effective for reducing power consumption of the radio systems.
Further, it is well known that a differential amplifier circuit, a mixer circuit, and a variable gain amplifier circuit each are required to have a characteristic of low distortion to suppress an interference to an adjacent channel and deterioration in bit error rate caused by its inputting of disturbance waves.
However, the demands for lower supply voltage of portable equipment results in narrowing of its dynamic range for input/output signals, conflicting with the demands for lower distortion of the portable equipment. For this reason, it is very difficult to satisfy these two demands at the same time.
For these demands, a differential amplifier circuit improved in non-linearity (first conventional differential amplifier) is reported in a paper M. Koyama et. al., xe2x80x9cA 2.5-V Active Low-Pass Filter Using All -n-p-n Gilbert Cells with a 1-Vp-p Linear Input Rangexe2x80x9d (IEEE J. Solid State Circuits, Vol., SC-28, No. 12, pp. 1246-1253, Dec. 1993).
Further, a differential amplifier circuit (second conventional amplifier circuit) enabling the first conventional differential amplifier circuit to operate at low voltage is disclosed, for example, in Japanese Patent Laid-Open No. 8-250941.
Hereinafter, these conventional circuits will be described. First, the first conventional differential amplifier will be described.
FIG. 2 shows the first conventional differential amplifier circuit which is shown in the report xe2x80x9cA 2.5-V Active Low-Pass Filter Using All -n-p-n Gilbert Cells with a 1-Vp-p Linear Input Rangexe2x80x9d.
Referring to FIG. 2, the first conventional differential amplifier circuit comprises two input terminals 51 and 52, two operational amplifiers 53 and 54 having the positive inputs connected to the input terminals 51 and 52 respectively, NPN transistors 71 and 72 having the bases connected to each output of the operational amplifiers 71 and 72 respectively, constant current sources 91 and 92 connected between each emitter of the transistors 71 and 72, and a ground terminal 58 respectively, a feedback resistor 81 connected between the emitters of the transistors 71 and 72, and load resistors 82 and 83 connected between each collector of the transistors 71 and 72 and a power supply terminal 57 respectively, wherein each emitter of the transistors 71 and 72 is connected to each negative input of the operational amplifiers 53 and 54 respectively, and each collector of the transistors 71 and 72 is connected to each of output terminals 61 and 62 respectively.
The first conventional differential amplifier circuit configured as described above operates as follows.
That is, in the first conventional differential amplifier circuit, a input voltage Vin inputted between a pair of the input terminals 51 and 52 is directly applied across the feedback resistor 81 through a pair of voltage follower circuits consisting of a set of the operational amplifier 53 and the transistor 71 and a set of the operational amplifier 54 and the transistor 72. Herein, since the feedback resistor 81 is a linear element, a linear current flows through the resistor 81 according to a voltage applied across the resistor.
In the circuit of FIG. 2, the resistance value of the feedback resistor 81 is represented as RFB1 and a signal current flowing through the feedback resistor 81 is represented as i. Then, the relation between RFB1 and i can be expressed by the following equation.
i=(Vin/RFB1)xe2x80x83xe2x80x83(1)
A current given by the equation (1) flows through the respective emitters of the transistors 71 and 72 as a positive current and a negative current, respectively. Further, if the base currents flowing through the transistors 71 and 72 can be neglected because of the high current gain of the transistors, their emitter currents are equal to their collector currents. Therefore, the linear current given by the equation (1) is supplied through the load resistors 82 and 83.
Herein, clearly from the equation (1), the transconductance Gm of the differential amplifier circuit of FIG. 2 can be expressed by the following equation.
Gm=(i/Vin)=(1/RFB1)xe2x80x83xe2x80x83(2)
Further, the above respective collector currents are converted into the corresponding voltages through the load resistors 82 and 83 inserted between each collector of the transistors 71 and 72 and the power supply terminal 57, and the resultant voltages are outputted to output terminals 61 and 62.
By representing the resistance values of the load resistors 82 and 83 as RC, the voltage gain G of the differential amplifier circuit of FIG. 2 can be expressed by the following equation, using equation (2).
G=Gmxc2x7Rc=(Rc/RFB1)xe2x80x83xe2x80x83(3)
On the other hand, when the current values of the constant current sources 91 and 92 each are represented as I0, the linear Input Dynamic Range (IDR) of the differential amplifier circuit of FIG. 2 can be expressed by the following equation.
IDR=I0xc2x7RFB1xe2x80x83xe2x80x83(4)
Also, the dc potential V0 (DC) of the output terminals can be expressed by the following equation.
V0(DC)=Vccxe2x88x92I0xc2x7Rcxe2x80x83xe2x80x83(5)
As described above, the first conventional differential amplifier circuit can provide a linear output voltage according to an input voltage Vin without being affected by the non-linearity of the differential pair of the input transistors 71 and 72.
FIG. 3 shows an example of the relations of input voltage (Vin) and transconductance (Gm) and output current (io, iob) for the first conventional differential amplifier circuit shown in FIG. 2. In addition, FIG. 3 also shows the relations of input voltage versus transconductance and output current for a most basic differential amplifier circuit with an emitter feedback resistor shown in FIG. 1.
In the example of FIG. 3, the resistance value RFB1 of the feedback resistor 81 is assumed to be 2000xcexa9 and the currents I0 of the constant current sources 91 and 92 each are assumed to be 0.45 mA. It can be seen from FIG. 3 that the first conventional differential amplifier circuit is superior in linearity to the differential amplifier circuit with an emitter feedback resistor shown in FIG. 1.
The circuit diagram of FIG. 4 shows a configuration of the first conventional differential amplifier circuit and the potential of each node therein. Herein, only a half of the circuit is shown because of the symmetry of the differential amplifier circuit.
Therein, the base of a transistor 531, the base and the collector of a transistor 532 serve as a positive input, a negative input and an output of the operational amplifier 53 respectively, and the transistor 71 configures a voltage follower circuit. For this reason, when the potential of the input terminal 51 is represented as Vin, the base potential of the transistor 532 is also Vin, and therefore the base potential of the transistor 71 becomes (Vin+VBEQ71).
Next, the second conventional differential amplifier circuit will be described.
FIG. 5 shows the second conventional differential amplifier circuit shown in Japanese Patent Laid-Open No. 8-250941.
The second conventional differential amplifier circuit comprises, in addition to the first conventional differential amplifier circuit, transistors 77 and 78 connected in diode connection (collector and base are shorted ) and constant current sources 93 and 94 connected between each collector of the transistors 77 and 78 and the power supply terminal 57. Thus, when compared to the differential amplifier circuit shown in FIG. 2, the transistors 77 and 78 have the emitters connected to the emitters of the transistors 71 and 72 respectively, and the bases connected to the negative inputs of the operational amplifiers 53 and 54 respectively.
The second conventional differential amplifier circuit operates as described below.
That is, an input voltage Vin inputted between a pair of the input terminals 51 and 52 is shifted in dc voltage by the base-to-emitter voltage VBE of the diode-connected transistors 77 and 78 through a pair of voltage follower circuits, which are configured by the operational amplifier 53, transistor 71 and diode-connected transistor 77, and the operational amplifier 54, transistor 72 and diode-connected transistor 78. Then, the input voltage shifted is applied across the feedback resistor 81. Herein, since the feedback resistor 81 is a linear element, thus linear currents flow through the resistor according to the voltages applied across it.
In the second conventional differential circuit, the resistance value of the feedback resistor 81 is represented as RFB2 and a signal current flowing through the feedback resistor 81 is represented as i. Then, the relation between RFB1 and i can be expressed by the following equation.
i=(Vin/RFB2)xe2x80x83xe2x80x83(6)
A current given by the equation (6) flows through each emitter of the transistors 71 and 72 as a positive current and a negative current, respectively. Further, if the same assumption as in the first conventional circuit is made, the emitter currents of the transistors 71 and 72 are equal to their collector currents. Therefore, the linear current given by the equation (6) is supplied to the load resistors 82 and 83.
Herein, clearly from the equation (6), the transconductance Gm of the differential amplifier circuit of FIG. 5 can be expressed by the following equation.
Gm=(i/Vin)=(1/RFB2)xe2x80x83xe2x80x83(7)
Further, the above collector currents are converted into the corresponding voltages through the load resistors 82 and 83 connected between each collector of the transistors 71 and 72 and the power supply terminal 57, and the resultant voltages are output to output terminals 61 and 62.
By representing the resistance values of the load resistors 82 and 83 as RC, the voltage gain G of the differential amplifier circuit of FIG. 5 can be expressed by the following equation.
G=Gmxc2x7Rc=(Rc/RFB2)xe2x80x83xe2x80x83(8)
On the other hand, when each current value of the constant current sources 91 and 92 is assumed to be 2I0 and each current value of the constant current sources 93 and 94 is assumed to be I0, the linear Input Dynamic Range (IDR) of the differential amplifier circuit of FIG. 5 can be expressed by the following equation (9).
IDR =I0xc2x7RFB2xe2x80x83xe2x80x83(9)
Also, the dc potential V0 (DC) of the output terminals can be expressed by the following equation.
V0(DC)=Vccxe2x88x92I0xc2x7Rcxe2x80x83xe2x80x83(10)
As described above, the second conventional differential amplifier circuit also can provide linear output voltages according to input voltages Vin without being affected by the non-linearity of the differential pair of the input transistors 71 and 72, in the same manner as the first conventional differential amplifier.
FIG. 6 shows an example of the relations of input voltages (Vin) versus transconductance (Gm) and output current (io, iob) for the second conventional differential amplifier circuit shown in FIG. 5.
In the example of FIG. 6, the resistance value RFB2 of the feedback resistor 81 is assumed to be 2000xcexa9, the currents of the constant current sources 91 and 92 are assumed to be 2I0, and the currents of the constant current sources 93 and 94 are assumed to be I0, wherein I0 is assumed to be 0.45 mA.
By the way, the difference between the first and second conventional circuits is in that the diode-connected transistors 77 and 78 are inserted between the emitters of the transistors 71 and 72 and the negative inputs of the operational amplifiers 53 and 54.
Next, the effect of these diode-connected transistors 77 and 78 will be described.
The circuit diagram of FIG. 7 shows a configuration of the second conventional circuit and the potential of each node therein. Herein, only a half of the circuit is shown because of the symmetry of the differential amplifier circuit.
Therein, the base of a transistor 531, the base and the collector of a transistor 532 serve as a positive input, a negative input and an output of the operational amplifier 53, respectively, and a voltage follower circuit is configured by the transistors 71 and 77. For this reason, when the potential of the input terminal 51 is represented as Vin, the base potential of the transistor 532 is given as Vin, and the emitter potential of the transistor 77 is given as Vinxe2x88x92VBEQ77. Therefore, the base potential of the transistor 71 is then given as Vinxe2x88x92VBEQ77+VBEQ71.
Further, because the base-to-emitter voltage VBE of transistors can be considered to be approximately constant, the base potential of the transistor 71 becomes equal to Vin. On the other hand, in the case of the first conventional differential amplifier circuit, because the diode-connected transistor 77 is not included therein, the emitter potential of the transistor 71 is Vin and the base potential thereof is Vin+VBEQ71. Thus, the base potential of the transistor 71 is higher by one stage of VBE as compared with the second conventional differential amplifier circuit.
This fact means that the second conventional differential amplifier circuit can be operated at lower voltage than the first conventional differential amplifier circuit.
However, the above conventional differential amplifier circuits have the following problem.
That is, in attempting to apply the differential amplifier circuit of FIG. 5 to a mixer circuit and a variable gain amplifier circuit, then a configuration of three vertical stacks of NPN transistors is required, thus causing a problem that high gain can not be obtained during low voltage operation.
Hereinafter, the reason for the occurrence of the above problem will be described with reference to figures.
FIG. 8 shows a circuit configuration for applying the second conventional differential amplifier circuit to a mixer circuit.
The mixer circuit shown in FIG. 8 comprises, in addition to the differential amplifier circuit shown in FIG. 5, two differential pairs of transistors 73, 75 and 74, 76 where each pair of transistors have the emitters connected to each other, and a set of local oscillator signal input terminals 63 and 64, wherein the input terminal 63 is connected to the commonly-connected bases of the transistors 73 and 74 and the input terminal 64 is connected to the commonly-connected bases of the transistors 75 and 76.
Also, the collector of the transistor 73 is connected to the collector of the transistor 76 and the collector of the transistor 74 is connected to the collector of the transistor 75, and the commonly-connected emitters of the transistors 73 and 75 are connected to the collector of the transistor 71 and the commonly-connected emitters of the transistors 74 and 76 are connected to the collector of the transistor 72.
Further, the commonly-connected collectors of the transistors 73 and 76 are coupled to the power supply terminal 57 through a load resistor 82 and the commonly-connected collectors of the transistors 74 and 75 are coupled to the power supply terminal 57 through a load resistor 83.
The conversion gain CG of the mixer circuit using this second conventional differential amplifier circuit can be calculated in the same manner as the gain of double balanced mixers used widely in general.
That is, if the dual differential pairs of transistors in double balanced mixers are switching operated by a local oscillator signal, the following equation is held between the gain G of the differential amplifier circuits and the conversion gain CG of the mixer circuit therein.
CG=(2/xcfx80)xc2x7Gxe2x80x83xe2x80x83(11)
Therefore, the conversion gain CG of the mixer circuit using the second conventional circuit can be expressed by the following equation from the equations (8) and (11).
CG=(2/xcfx80)xc2x7(Rc/RFB2)xe2x80x83xe2x80x83(12)
Herein, it can be understood from the equation (12) that increased values of the conversion gain CG require increased resistance values Rc of the load resistors 82 and 83. For this reason, it can be understood that the base potential of the transistor 73 (or 74, 75, 76) is preferably lower.
Therefore, the lowest base potential of the transistor 73 (or 74, 75, 76) will be determined. The circuit diagram of FIG. 9 shows each potential of the nodes in the mixer circuit of FIG. 8. Herein, only a half of the circuit is shown in FIG. 9 because of the symmetry of the differential amplifier circuit. Further, for the purpose of simplicity, the voltage drops developed across emitter resistors of constant current supply transistors will be neglected.
First, when Vin is lowest, the conditions under which constant current supply transistors 533 and 911 can not be saturated are expressed by the following equations.
Vin (min) greater than VCE(sat)Q533+VBEQ531xe2x80x83xe2x80x83(11a)
Vin (min) greater than VCE(sat)Q911+VBEQ71xe2x80x83xe2x80x83(11b)
Therefore, the lowest input voltage Vin (min) can be expressed by the following equation from the equations (11a) and (11b) However, because emitter-to-base voltages VBE of transistors can be considered to be approximately constant, the equations (11a) and (11b) are considered to be equal.
Vin (min)=VCE(sat)Q533+VBEQ531xe2x80x83xe2x80x83(11c)
Next, when Vin is highest, the condition under which the transistor 71 can not be saturated is given by the following equation.
VLO greater than Vin (max)xe2x88x92VBEQ71+VCE(sat)Q71+VBEQ73xe2x80x83xe2x80x83(13)
Therefore, the lowest base potential of the transistor 73 can be expressed by the following equation from the equation (13).
VLO=Vin (max)xe2x88x92VBEQ71+VCE(sat)Q71+VBEQ73xe2x80x83xe2x80x83(14)
Further, when the voltage of the power supply is assumed to be Vcc, the range of output voltages xcex94V0 is given by the following equation.
xcex94V0=Vccxe2x88x92(VLOxe2x88x92VBEQ73+VCE(sat)Q73)=Vccxe2x88x92(Vin (max)xe2x88x92VBEQ71+VCE(sat)Q71+VBEQ73xe2x88x92VBEQ73+VCE(sat)Q73)xe2x80x83xe2x80x83(15)
On the other hand, in order to prevent the saturation of the transistors caused by decreased voltage and temperature variations, it is also desirable that the dc potential of output signals is set at the center of the output voltage range xcex94V0 given the equation (15) so as to provide the widest range of linear output voltage.
This fact requires the relations expressed by the two following equations.
(xcex94V0/2)=I0xc2x7Rcxe2x80x83xe2x80x83(16)
CG=(2/xcfx80)xc2x7(I1/RFB2)xc2x7(xcex94V0/2I0)xe2x80x83xe2x80x83(17)
Herein, assuming that the power supply voltage Vcc is 1.8 V, the input voltage Vin is 0.5 Vp-p, and the base-to-emitter voltage VBE and the collector-to-emitter saturation voltage VCE(sat) of the transistors are constant voltages of 0.7 V and 0.15 V respectively, first from equation (11c), the minimum value Vin (min) of the input voltages is expressed by the following equation.
Vin (min)=0.15+0.7=0.85xe2x80x83xe2x80x83(18)
Also, the maximum value Vin (max) of the input voltages is expressed by the following equation.
Vin (max)=Vin (min)+Vin=0.85+0.5=1.35xe2x80x83xe2x80x83(19)
Then, by substituting the value of the equation (19) into the equation (14), the minimum base potential of the transistor 73 can be obtained as the following value.
VLO=1.35xe2x88x920.7+0.15+0.7=1.5xe2x80x83xe2x80x83(20)
Further, by substituting the values of the equations (18) and (19) into the equation (15), the output voltage range xcex94V0 is obtained as the following value.
xcex94V0=1.8xe2x88x92(1.35xe2x88x920.7+0.15+0.7xe2x88x920.7+0.15)=0.85xe2x80x83xe2x80x83(21)
That is, the output voltage range xcex94V0 is becomes 0.85 Vp-p, meaning that the output voltage range is, at most, only 47% of the power supply voltage Vcc.
Further, assuming that RFB2 is 2000xcexa9 and I0 is 0.45 mA, the conversion gain CG obtained is only the order of about 0.300 (times).
The invention has been performed in views of such circumstances, and it has an object to provide a differential amplifier circuit having low distortion, which can provide high voltage gain even during low voltage operation when used for mixer circuits and variable gain amplifier circuits.
The invention has another object to provide a differential amplifier circuit having low distortion applicable to a three-input mixer circuit that is not operated at low voltage.
An object of the invention is to improve the above-described drawbacks of the conventional technologies and to provide a differential amplifier circuit having low distortion, which can provide high voltage gain even during low voltage operation particularly when used for mixer circuits and variable gain amplifier circuits.
Another object of the invention is to provide a differential amplifier circuit having low distortion applicable to a three-input mixer circuit that is not operated at low voltage.
According to the invention, the differential amplifier circuit comprises a first and second input terminals,
a first and second operational amplifiers whose negative inputs are connected to each of the first and second input terminals respectively,
a first and second transistors whose bases are connected to each output of the first and second operational amplifiers respectively,
a first and second constant current sources connected between each emitter of the first and second transistors and a ground terminal respectively,
a third and fourth constant current sources connected between each collector of the first and second transistors and a power supply terminal respectively,
a first resistor connected between the collectors of the first and second transistors, and
a pair of transistors having the emitters connected to each emitter of the first and second transistors and the bases connected to each other, wherein the collectors of the first and second transistors are connected to the positive inputs of the first and second operational amplifiers respectively,
the commonly-connected bases of the pair of transistors are connected to input terminals for inputting a predetermined signal, and
the collectors of the pair of transistors form a set of output terminals and output a set of output currents from the set of output terminals according to an input voltage applied between the first and second input terminals.
Further, all the transistors included in the differential amplifier circuit according to the invention are configured by NPN transistors.
Also, according to the invention, the mixer circuit comprises a first and second input terminals,
a first and second operational amplifiers whose negative inputs are connected to each of the first and second input terminals respectively,
a first and second transistors whose bases are connected to each output of the first and second operational amplifiers respectively,
a first and second constant current sources connected between each emitter of the first and second transistors and a ground terminal respectively,
a third and fourth constant current sources connected between each collector of the first and second transistors and a power supply terminal respectively,
a first resistor connected between the collectors of the first and second transistors,
a pair of transistors having the emitters connected to each emitter of the first and second transistors and the bases connected to each other, and
a fifth and sixth transistors whose bases are connected to each other, wherein the collectors of the first and second transistors are connected to the positive inputs of the first and second operational amplifiers respectively,
the commonly-connected bases of the pair of transistors are connected to input terminals for inputting a predetermined signal, and
the commonly-connected bases of the fifth transistor and the sixth transistor, together with the commonly-connected bases of a third and fourth transistors forming the pair of transistors, are connected to a set of local oscillator signal input terminals, and the collectors of the third and fourth transistors are connected to the collectors of the sixth transistor and the fifth transistor respectively and also coupled to the power supply terminal through a first and second load resistors respectively.
Further, the mixer circuit according to the invention can be adapted for various suitable application forms described below.
That is, according to the invention, the mixer circuit may further have a seventh and eighth transistors whose bases are connected to each other, and
a ninth and tenth transistors whose bases are connected to each other, wherein the commonly-connected bases of the seventh and eighth transistors and the commonly-connected bases of the ninth and tenth transistors each are connected to a set of second local oscillator signal input terminals,
each collector of the seventh and eighth transistors is connected to each collector of the tenth and ninth transistors respectively and also coupled to the power supply terminal through the first and second load resistor respectively,
the emitters of the seventh and ninth transistors are connected to each other and also connected to the collector of the fifth transistor,
the emitters of the eighth and tenth transistors are connected to each other and also connected to the collector of the sixth transistor,
the collectors of the seventh and eighth transistors are connected to output terminals and output from the output terminals an output voltage mixed according to an input voltage between the input terminals of the first and second input terminals, a local oscillator signal input from the set of local oscillator signal input terminals and a second local oscillator signal input from the second local oscillator signal input terminals.
Also, according to the invention, all the transistors included in the mixer circuit can be configured by NPN transistors.
Further, according to the invention, the variable gain amplifier circuit comprises a first and second input terminals,
a first and second operational amplifiers whose negative inputs are connected to each of the first and second input terminals respectively,
a first and second transistors whose bases are connected to each output of the first and second operational amplifiers respectively,
a first and second constant current sources connected between each emitter of the first and second transistors and a ground terminal respectively,
a third and fourth constant current sources connected between each collector of the first and second transistors and a power supply terminal respectively,
a first resistor connected between the collectors of the first and second transistors, and
a pair of transistors having the emitters connected to each emitter of the first and second transistors and the bases connected to each other, and
a fifth and sixth transistors whose bases are connected to each other, wherein the collectors of the first and second transistors are connected to the positive inputs of the first and second operational amplifiers respectively,
the commonly-connected bases of the pair of transistors are connected to input terminals for inputting a predetermined signal, and
the commonly-connected bases of the fifth and sixth transistors, together with the commonly-connected bases of a third and fourth transistors forming the pair of transistors, are connected to a set of gain control signal input terminals, and each collector of the third and fourth transistors are connected to the power supply terminal respectively,
the collector of the fifth transistor is coupled to the power supply terminal through the first load resistor and also connected a first output terminal, and the collector of the sixth transistor is coupled to the power supply terminal through the second load resistor and also connected to a second output terminal, and, in addition, a gain control signal is input to the set of input terminals instead of the local oscillator signal.
Also, according to the invention, all the transistors included in the variable gain amplifier circuit may be configured by NPN transistors.
Further, according to the invention, the differential amplifier circuit comprises a first and second input terminals, a first and second operational amplifiers whose negative inputs are connected to each of the first and second input terminals respectively,
a first and second transistors whose gates are connected to each output of the first and second operational amplifiers respectively,
a first and second constant current sources connected between each source of the first and second transistors and a ground terminal respectively,
a third and fourth constant current sources connected between each drain of the first and second transistors and a power supply terminal respectively,
a first resistor connected between the drains of the first and second transistors, and
a pair of transistors having the sources connected to each source of the first and second transistors respectively and the gates connected to each other, wherein the drains of the first and second transistors are connected to the positive inputs of the first and second operational amplifiers respectively,
the commonly-connected gates of the pair of transistors are connected to input terminals for inputting a predetermined signal, and
the drains of the pair of transistors form a set of output terminals and output a set of output currents from the set of output terminals according to an input voltage applied between the first and second input terminals.
Also, according to the invention, all the transistors included in the differential amplifier circuit may be configured by N type field effect transistors.